Automatic underwater null steering

ABSTRACT

Means are provided for reducing the dynamic range requirement of an  underer sound system by minimizing the effects of noise interference. Computer means are provided to automatically rotate the pattern function of the combination of the dipole hydrophones in the system. A minimum noise pattern position is derived from hydrophone output information.

BACKGROUND OF THE INVENTION

The invention is in the field of underwater sound transmission systems. One example of such systems is an array of hydrophones arranged to receive underwater sound energy and which is directionally sensitive to the angle of arrival of an impinging sound wave. Such arrays are commonly employed in sonar systems.

In such systems of the prior art interfering noise at the hydrophones can cause clipping nonlinearities in the system, greatly degrading performance. It is known that the effect of such interference can be reduced by combining the outputs of dipole hydrophones positioned orthogonally with respect to each other in such manner that the resulting dipole pattern can be steered to achieve a null. The invention overcomes the deficiencies of the prior art by providing means for automatically computing a null position and rotating the pattern function of the combination of two dipole hydrophones to such position to minimize noise in the system.

SUMMARY OF THE INVENTION

The invention increases the dynamic range of an underwater sound transmission system by weighting the outputs of a pair of dipole hydrophones with a value designed to minimize noise interference in the transmission system input. A specialized analog computer processes the output signals from the hydrophones, which have mutually orthogonal sensitivity patterns, to derive the weighting values. The computer has two inputs from the hydrophones, ##EQU1## N (φ) being a directionality factor involving the approach angle φ of an underwater soundwave.

The computer calculates two output values, sin φ_(o) and cos φ_(o) which are used to weight the hydrophone outputs. φ_(o) is an angle at which the sensitivity pattern of the combination of the hydrophones nulls to minimize noise in the transmission system input.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an arrangement for minimizing the noise output of steered dipole hydrophones.

FIG. 2 shows details of an analog computer for computing the values sin φ_(o) and cos φ_(o) used in the apparatus of FIG. 1.

FIG. 3 shows a simplified computer useful in situations where only one noise source is encountered.

FIG. 4 is a graph illustrating the relationship between the output pattern after null steering and noise directionality as a function of azimuth.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 shows an underwater sound transmission system having two dipole hydrophones D₁ and D₂ which are co-located and have mutually orthogonal sensitivity patterns. The arrangement is such that the expected output power P₁ of hydrophone D₁ is ##EQU2## The expected output power P₂ of hydrophone D₂ is ##EQU3## Here φ is the azimuthal variable, that is the azimuth of the noise sources which generate noise impinging on hydrophones D₁ and D₂. N (φ) is the noise directionality function.

The expected power output P_(o) at an output terminal 12 is ##EQU4## where φ_(o) is the azimuthal angle of a hypothetical sound wave arriving at hydrophones D₁ and D₂ but producing no output power at terminal 12 because of the circuit. P_(o) has nulls in the φ_(o) and the (φ_(o) +π) directions.

Nulls in the sensitivity pattern of P_(o) are automatically steered to the position which minimizes noise power in the signal V_(o). In effect, nulls are steered by adding weighted outputs of D₁ and D₂.

The output signal V₁ of hydrophone D₁ is multiplied by a factor sin φ_(o) in a multiplier 2. The quantity V₁ sin φ_(o) is inverted in an amplifier 8 and added to a quantity V₂ cos φ_(o) in a summing circuit 10 which generates the output V_(o) of the circuit of FIG. 1 on terminal 12. The value V₂ cos φ_(o) is derived from hydrophone D₂ and a multiplier 4 which has a cos φ_(o) input from an output of a control 6.

Control 6 is connected to receive the outputs of D₁ and D₂ and to generate the value sin φ_(o) and cos φ_(o) which are furnished to multipliers 2 and 4. To minimize noise in the output of the circuit of FIG. 1 it is necessary for control 6 to compute those values of cos φ_(o) and sin φ_(o) which will minimize P_(o). It is necessary for control 6 to find the zero of ##EQU5##

If N (φ) is expanded in a Fourier series on the interval (0, 2π) only the second harmonic will contribute to the integral in equation (4) and without loss of generality, N (φ) can be written

    N(φ)=Q+R cos (2φ+φ.sub.1)                      (5)

where R is the maximum power level of the second harmonic component of N (φ).

Substituting equation (5) into equation (4), integrating and simplifying results in

    sin (φ.sub.1 -2φ.sub.o)=0                          (6)

from which ##EQU6##

Equations (7) and (8) are the values for sin φ_(o) and cos φ_(o) required to be generated by control 6 to minimize the noise at output terminal 12.

FIG. 2 illustrates the arrangement of the control 6 in FIG. 1. Control 6 is an analog computer which computes the values of sin φ_(o) and cos φ_(o) required to minimize noise at output terminal 12 of FIG. 1. In FIG. 2 dipole hydrophones D₁ and D₂ furnish output signals to a summing circuit 16. The output of D₁ is inverted in an inverter 18 which supplies an input to a summing circuit 20. The output of D₂ is furnished as a second input to 20. The sum outputs of 16 and 20 are multiplied in a multiplier 22 to obtain a product which is integrated in an integrating circuit 24 to obtain the quantity ∫N cos 2 φ d φ which is supplied to a dividing circuit 26. The output of 26 is controlled also by a value R which is obtained by passing the output of a summing circuit 28 through a square root extracting circuit 30. One input to summing circuit 28 is derived by squaring the output of integrator 24 in a squaring circuit 32. A second input to summing circuit 28 is derived by squaring the output of an integrating circuit 34 in a squaring circuit 36. The input to integrator 34 is the output of a multiplier 38 which has as inputs the outputs from D₁ and D₂.

The output of dividing circuit 26 is halved in a dividing circuit 40 and applied to a summing circuit 42 and through an inverter 19 to a summing circuit 44. A second input to each of circuits 42 and 44 furnishes the quantity 1/2 to be summed with the output of 40. The outputs of 42 and 44 are furnished to two respective square root circuits 46 and 48 which furnish the output values sin φ_(o) and cos φ_(o) to two multiplying circuits 50 and 52. See equations (8) and (9). 50 and 52 receive the outputs of dipole hydrophones D₁ and D₂ respectively. The outputs of 50 and 52 are summed in an output summing circuit 54 to obtain a system output signal V₀₂. The output of 50 is inverted in an inverter 56 and summed with the output 52 in a second output summing circuit 58 to obtain a second system output signal V₀₁ which is 90° out of phase with V₀₂. Means not shown, for example a known comparator circuit, are provided to select the smaller of the two system outputs.

If only one interfering noise source N_(J) (φ) is expected, then a simpler apparatus than that of FIG. 2 may be used. The simplification follows from the approximation that, in the presence of N_(J) (φ), the total power is dominated by N_(J) (φ) so that

    P.sub.o =∫N.sub.J (φ) sin.sup.2 (φ-φ.sub.o)dφ(9)

Since the interference is assumed to come from a single direction, say φ₁, then

    N.sub.J (φ)=Mδ(φ-φ.sub.1)                (10)

where M is the interference strength. These assumptions lead to the simplified expressions

    sin.sup.2 φ.sub.o =∫N(φ) sin.sup.2 φdφ/∫N(φ)dφ                          (11)

and

    cos.sup.2 φ.sub.o =∫N(φ) cos.sup.2 (φ)dφ/∫N(φ)d(φ)                      (12)

These expressions are implemented by the simplified apparatus shown in FIG. 3, where the output signals from hydrophones D₁ and D₂ go to two squaring circuits 60 and 62. The outputs of 60 and 62 are integrated in two respective integrating circuits 64 and 66. The outputs of 64 and 66 go to a summing circuit 68 and to two dividing circuits 70 and 72. The output of summing circuit 68 controls an AGC circuit 74 which has two outputs connected to dividing circuits 70 and 72. The outputs of 70 and 72 are connected to two respective square root circuits 80 and 82 to obtain sin φ_(o) and cos φ_(o) outputs which are forwarded to two multipliers 76 and 78. As in the apparatus of FIG. 2 an inverter 56 and two summing circuits 54 and 58 are provided to obtain the system output.

FIG. 4 shows the relationship of the dipole sensitivity pattern after null steering to power and to the second harmonic of N (φ). The terms "R, φ, φ_(o), and φ₁ " are graphically illustrated. As shown in FIG. 4, R is equal to the maximum magnitude of the second harmonic of N (φ) and φ_(o) is equal to 1/2 of φ₁. 

What is claimed is:
 1. In an underwater sound transmission system, the improvement comprising:a pair of dipole hydrophones, said hydrophones being positioned so that their sensitivity patterns are orthogonal with respect to each other, each of said hydrophones being adapted to receive sound energy approaching at an angle φ to develop a hydrophone output signal V, said system developing an output signal V_(o) in response to said hydrophone output signals V, computing means connected to receive said hydrophone output signals V, said computing means being adapted to derive functions of an angle φ_(o) from said signals V, a pair of multiplying means for multiplying each hydrophone output signal V by a respective function of φ_(o) to generate a pair of product signals V₁ sin φ_(o) and V₂ cos φ_(o), combining means connected to said multiplying means to combine said product signals into the system output signal V_(o), the angle φ_(o) being such that interference noise in said output signal V_(o) is automatically minimized, said combining means including inverting means for inverting a product signal V f (φ_(o)), said combining means including summing means for summing said product signals V f (φ_(o)), said summing means including, a first summing circuit for summing one of said product signals V₂ cos φ_(o) and an inverted product signal -V₁ sin φ_(o) to derive a first system output signal V₀₁, and a second summing circuit for summing two of said product signals V₂ cos φ_(o) and V₁ sin φ₂ to produce a second system output signal V₀₂.
 2. The apparatus of claim 1, said computing means including,means for squaring said hydrophone output signals V, means for integrating the squares of output signals V, and means for combining the integrals of the squared output signals V to obtain signals sin φ_(o) and cos φ_(o).
 3. The apparatus of claim 1, said computing means including,a first multiplying means 38 for multiplying the output signals V₁ and V₂ of a pair of said hydrophones D₁ and D₂, a first integrating means 34 for integrating the output of said multiplying means, a first squaring means 36 for squaring the output of said first integrating means, a first summing means 16 for summing the outputs V₁ and V₂ of said hydrophones D₁ and D₂, a first inverting means 18 for inverting a first of said hydrophone output signals V₁, a second summing means 20 for summing the inverted first hydrophone output signal -V₁ and the second hydrophone output signal V₂, a second multiplying circuit 22 for multiplying output signals from said first and second summing circuits, a second integrating circuit 24 for integrating an output signal from said second multiplying circuit 22, a second squaring circuit 32 for squaring an output signal from said second integrating circuit 24, a third summing circuit 28 for summing output signals from said first and said second squaring circuits 36 and 32, a first square root circuit 30 for deriving the square root of an output signal from said third summing circuit 28, a dividing circuit 26 for combining the outputs of said second integrating circuit 24 and said first square root circuit 30, a dividing circuit 40 for halving the output of said dividing circuit 26, a fourth summing circuit 42 for adding one-half of the output of said dividing means 40, a second square root circuit 48 of deriving the square root of the output of said fourth summing circuit 46 to generate a value sin φ_(o), a fifth summing circuit 44 for adding one-half to the output of said dividing means, and a third square root circuit 48 for deriving the square root of the output of said fifth summing circuit 44 to generate a value cos φ_(o). 